Modern communication systems are pushing the analog-to-digital converters (ADCs) toward high sampling rate,high resolution,high spurious-free dynamic range (SFDR) and low power.Because of outstanding performance of the pipelined ADCs they are the mainstream of high speed,high resolution ADCs.The performance of sample and hold circuit which is in the front of ADC determines the performance of the whole ADC,whose design is a very important phase in the design of the whole ADC.Now the ADCs need to suffice higher requirement.This requires that the sample and hold circuit has high sampling rate,high resolution,high spurious-free dynamic range(SFDR) and low power.In this paper,first of all the research and development trends of sample and hold circuit is introduce.And then the basic theory of sample and hold circuit is dissertated and analyzed at length,the relationship between the pipelined ADC and the sample and hold circuit is explained,simultaneously.Afterward the basic structure of sample and hold circuit and several average structures are introduced.Based on the above introduction and analysis,a sample and hold circuit used in a 14 bit 250M sample/s pipelined ADC is designed.It uses a class AB amplifier architecture in a sampling gate,is differential open-loop structure.It contains four modules:input buffer,hold capacitance,output buffer,a clock circuit that generates a set of clock signals.Clamp circuit is used to eliminate feedthrough of the input signal during the hold mode in the sample and hold circuit.In order to improve the signal-to-noise-and-distortion ratio and effective number of bits,the bandwidth-limiting resistor limited the noise bandwidth is implemented in the front of hold capacitor.The value of the hold capacitor,the value of the bias current,the size and type of transistor are chosen optimally,this improves performance of the sample and hold circuit.After the schematic is finished,the layout of the circuit is designed.The sample and hold circuit is simulated by Cadence EDA software with Zarlink 0.6μm complementary bipolar process model.The sample and hold circuit is simulated under the conditions of power supply of 5V,input sinewave with frequency of 39.9609MHz and amplitude of 1V,the simulated results show the settling time is 1.55ns,the spurious free dynamic range(SFDR) is 92.81 dB,the signal-to-noise-and-distortion ratio(SNDR) is 92.28dB,the effective number of bits is 15 bits,the power dissipation is 39.76mW.So the sample and hold circuit reach the demands of ADC.