On the basis of the project "Theoretical Research and Design of Key Technique for Deep-submicron Power Management IC and Mixed IC", a systematic study of the principle and circuit design of high efficiency peak-current mode synchronous step-down regulator integrated circuit With LDO Mode is presented. The whole chip is simulated by HSPICE with 0.5μm BiCMOS model, and the simulation results meet the prospective design specification.First the basic theory of inductance DC-DC switching regulator and linear regulator is introduced, and then some important techniques are discussed, such as feedback control mode of switching regulator, technique of low power dissipation and high efficiency, technique of current sensing and so on. Next a interior frequency compensation strategy is used to make sure the stability of the voltage-loop of the Buck DC-DC switching regulator, and saves PCB area; also a special slope compensation technique is adopted to improve the stability of the current-loop of the switching regulator. Then some important sub-blocks are introduced. Finally, the simulation results of the whole chip are given.A Buck DC-DC switching regulator and a linear regulator are integrated in the monolithic integrated circuit chip. By adopting the technique of peak-current mode PWM control and synchronous rectification, the efficiency of the chip is up to 95%. The chip will work in PWM Mode at heavy and medium load while in LDO Mode at light load, which implements optimization and combination between low noise and high efficiency and can save the cost for application.