As a standard technique of test and Design-for-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment .And JTAG which is not only save much expense and time on PCB design, urges the development of design for testability of VISL circuit, and still also provide effective and convenient way for the "download" of registers chips.JTAG, IEEE-1149.1 is standard, which just realize the debug function only by five pins. It can test macro cells in the chip, test all kinds of IC chips and test the responding PCBs.By summarizing some literatures about Boundary Scan Test (BST), the background and present condition are first discussed in the thesis.Then discuss about the basic principle and structure of JTAG. And analyse the instruction.realized the logic design using Verilog HDL hardware language.Finally, building the testbanch, do the function verification and wave simulation.The thesis focuses on JTAG standard, and it is innovative that the design of the TAP controller in JTAG and doing the function verification and wave simulation.