System-on-a-chip(SOC) requires the integration of analog circuits and digital circuits on a single chip. The technology compilable, performance optimized A/D converter (ADC) is an very important block as the bridge of the analog world to the digital section in SOC. It is important and necessary to research ADC with high speed, high resolution, low power dissipation.The pipelined ADC has been widely researched and used. It isn't a basic architecture ADC, but it has achieved high performance in high resolution, high speed and low power consume compared with others. It has been a main leaguer of high speed, high resolution ADCs.The circuits designed here are based on 5V Si complementary bipolar process. Considering the compatibility with CMOS digital circuits, the digital output buffers is supplied with 3.3V. In this design, the key modules of pipelined ADC are introduced. The ADC is 3 stages for 5bits, 5bits, 4bits resolution each stage. Its advantages include high resolution, high speed, low power consume and so on. The main work I do here includes several aspects: a simple and effective T/H (track and hold) circuit and a bandgap voltage reference are designed; a sub_ADC with folding structure is designed here. Not only reducing the number of comparators, the sub_ADC also accomplishes the conversion from Gray code to Binary code, which makes the circuit more simple.These key modules have been simulated by Cadence Spectre software with standard Zarlink 0.6μm/5V Si complementary Bipolar process model. From the simulation results, we can see the circuits designed here can meet the demands of the 3 stage, 14 bit, 80Msamle/s pipelined A/D converter.